M68K Interpreter

Add the source operand to the destination operand and store the result in the destination location.

Add the source operand to the destination address register and store the result. The source is sign-extended before adding.

Add immediate data to the destination operand. Store the result in the destination operand.

Subtract the source operand from the destination operand and store the result in the destination location.

Subtract the source operand from the destination address register. Word operations are sign-extended to 32 bits prior to subtraction.

Subtract the immediate data from the destination operand. Store the result in the destination operand.

AND the source operand to the destination operand and store the result in the destination location.

AND the immediate data to the destination operand.

EOR (exclusive or) the source operand with the destination operand and store the result in the destination location.

EOR the immediate data with the contents of the destination operand. Store the result in the destination operand.

Calculate the logical complement of the destination and store the result. NOT performs bit-by-bit logical complementation.

OR the source operand to the destination operand, and store the result in the destination location.

OR the immediate data with the destination operand. Store the result in the destination operand.

The destination is cleared and loaded with all zeros. Cannot be used to clear an address register.

Exchange the contents of two registers. The entire 32-bit contents are exchanged. Supports data, address, and mixed exchanges.

Extend the least-significant byte in a data register to a word, or the least-significant word to a longword.

Move the contents of the source to the destination location. This is a copy operation; the source is not affected.

Move the contents of the source to the destination address register. If a word, it is sign-extended to a longword.

Subtract the destination operand from 0 and store the result in the destination location. Performs twos complement arithmetic subtraction.

Exchange the upper and lower 16-bit words of a data register.

Arithmetically shift the bits left. The shift count may be specified as a literal, register contents, or the value 1.

Arithmetically shift the bits right. The shift count may be specified as a literal, register contents, or the value 1.

Logically shift the bits left. A zero is shifted into the input position. The shifted-out bit is copied into the C and X bits of the CCR.

Logically shift the bits right. A zero is shifted into the input position. The shifted-out bit is copied into the C and X bits of the CCR.

Rotate the bits left. The extend bit X is not included in the operation. Bits shifted out at one end are shifted into the other end.

Rotate the bits right. The extend bit X is not included in the operation. Bits shifted out at one end are shifted into the other end.

Subtract the source operand from the destination operand and set the condition codes accordingly. The destination is not modified.

Subtract the source operand from the destination address register and set the condition codes. Supports word or longword operations.

Subtract the immediate data from the destination operand and set the condition codes accordingly. The destination is not modified.

Compare the operand with zero. No result is saved, but the CCR bits are set according to the result.

Program execution continues at the effective address specified by the instruction.

Jump to subroutine. Pushes the longword address of the next instruction onto the system stack (A7). Execution continues at the specified address.

Return from subroutine. The program counter is pulled from the stack. Used to terminate a subroutine and return to the calling code.

Branch always. Program execution continues at [PC] + displacement. Displacement is a twos complement value (8-bit or 16-bit).

Branch to subroutine. Pushes the next instruction address onto the stack (A7). Execution continues at [PC] + displacement.

Branch if equal (zero flag set). If condition is met, execution continues at [PC] + displacement.

Branch if not equal (zero flag clear). If condition is met, execution continues at [PC] + displacement.

Branch if greater than or equal (no overflow/negative mismatch). If condition is met, execution continues at [PC] + displacement.

Branch if greater than. If condition is met, execution continues at [PC] + displacement.

Branch if less than or equal. If condition is met, execution continues at [PC] + displacement.

Branch if less than. If condition is met, execution continues at [PC] + displacement.